cantyonion/opi-openwrt
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
opi-openwrt/package/boot/uboot-rockchip-rk3588/patches/101-Add-support-for-orangepi5.patch
baiywt c226e18bf1 Add support for Orange Pi 5
2023-04-26 17:50:41 +08:00

321 lines
7.1 KiB
Diff
Raw Blame History

From 9a5e2f804caf676d4bdec794d68afaa86a3ceb2d Mon Sep 17 00:00:00 2001
From: baiywt <baiywt_gj@163.com>
Date: Thu, 13 Apr 2023 10:30:00 +0800
Subject: [PATCH] Add support for orangepi5
---
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/rk3588s-orangepi-5-u-boot.dtsi | 127 ++++++++++++++++++++
arch/arm/dts/rk3588s-orangepi-5.dts | 44 +++++++
configs/orangepi-5-rk3588_defconfig | 99 +++++++++++++++
4 files changed, 272 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/rk3588s-orangepi-5-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3588s-orangepi-5.dts
create mode 100644 configs/orangepi-5-rk3588_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 97a48327..acafd995 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -171,7 +171,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
dtb-$(CONFIG_ROCKCHIP_RK3588) += \
rk3588-edgeble-neu6a-io.dtb \
- rk3588-rock-5b.dtb
+ rk3588-rock-5b.dtb \
+ rk3588s-orangepi-5.dtb
dtb-$(CONFIG_ROCKCHIP_RV1108) += \
rv1108-elgin-r1.dtb \
diff --git a/arch/arm/dts/rk3588s-orangepi-5-u-boot.dtsi b/arch/arm/dts/rk3588s-orangepi-5-u-boot.dtsi
new file mode 100644
index 00000000..7aca35ae
--- /dev/null
+++ b/arch/arm/dts/rk3588s-orangepi-5-u-boot.dtsi
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Collabora Ltd.
+ */
+
+#include "rk3588-u-boot.dtsi"
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ aliases {
+ mmc0 = &sdmmc;
+ };
+
+ chosen {
+ u-boot,spl-boot-order = &sdmmc, "same-as-spl";
+ u-boot,spl-boot-order = &sdmmc, "same-as-spl", &flash0;
+ };
+};
+
+&fspim2_pins {
+ u-boot,dm-spl;
+};
+
+&sdmmc {
+ bus-width = <4>;
+ bootph-all;
+ u-boot,spl-fifo-mode;
+ status = "okay";
+};
+
+&pcfg_pull_up_drv_level_2 {
+ bootph-all;
+};
+
+&pcfg_pull_up {
+ bootph-all;
+};
+
+&sdmmc_bus4 {
+ bootph-all;
+};
+
+&sdmmc_clk {
+ bootph-all;
+};
+
+&sdmmc_cmd {
+ bootph-all;
+};
+
+&sdmmc_det {
+ bootph-all;
+};
+
+&usb_host0_ehci {
+ companion = <&usb_host0_ohci>;
+ phys = <&u2phy2_host>;
+ phy-names = "usb2-phy";
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ phys = <&u2phy2_host>;
+ phy-names = "usb2-phy";
+ status = "okay";
+};
+
+&usb2phy2_grf {
+ status = "okay";
+};
+
+&u2phy2 {
+ resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
+ reset-names = "phy", "apb";
+ clock-output-names = "usb480m_phy2";
+ status = "okay";
+};
+
+&u2phy2_host {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ companion = <&usb_host1_ohci>;
+ phys = <&u2phy3_host>;
+ phy-names = "usb2-phy";
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ phys = <&u2phy3_host>;
+ phy-names = "usb2-phy";
+ status = "okay";
+};
+
+&usb2phy3_grf {
+ status = "okay";
+};
+
+&u2phy3 {
+ resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
+ reset-names = "phy", "apb";
+ clock-output-names = "usb480m_phy3";
+ status = "okay";
+};
+
+&u2phy3_host {
+ status = "okay";
+};
+
+&sfc {
+ bootph-all;
+ pinctrl-0 = <&fspim2_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ flash0: flash@0 {
+ bootph-all;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <1>;
+ };
+};
diff --git a/arch/arm/dts/rk3588s-orangepi-5.dts b/arch/arm/dts/rk3588s-orangepi-5.dts
new file mode 100644
index 00000000..cf5743bc
--- /dev/null
+++ b/arch/arm/dts/rk3588s-orangepi-5.dts
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "rk3588s.dtsi"
+
+/ {
+ model = "RK3588S Orange Pi 5";
+ compatible = "xunlong,orangepi5", "rockchip,rk3588";
+
+ aliases {
+ mmc0 = &sdhci;
+ serial2 = &uart2;
+ };
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+};
+
+&sdhci {
+ bus-width = <8>;
+ no-sdio;
+ no-sd;
+ non-removable;
+ max-frequency = <200000000>;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-0 = <&uart2m0_xfer>;
+ status = "okay";
+};
diff --git a/configs/orangepi-5-rk3588_defconfig b/configs/orangepi-5-rk3588_defconfig
new file mode 100644
index 00000000..782a4918
--- /dev/null
+++ b/configs/orangepi-5-rk3588_defconfig
@@ -0,0 +1,99 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
+CONFIG_DEFAULT_DEVICE_TREE="rk3588s-orangepi-5"
+CONFIG_DM_RESET=y
+CONFIG_ROCKCHIP_RK3588=y
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_MMC=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_TARGET_ROCK5B_RK3588=y
+CONFIG_SPL_STACK=0x400000
+CONFIG_DEBUG_UART_BASE=0xFEB50000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-rock-5b.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x20000
+CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x4000000
+CONFIG_SPL_BSS_MAX_SIZE=0x4000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_ROCKCHIP_SFC=y
+CONFIG_SYSRESET=y
+# CONFIG_BINMAN_FDT is not set
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_LAN75XX=y
+CONFIG_USB_ETHER_LAN78XX=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_ERRNO_STR=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
--
2.25.1
Reference in New Issue View Git Blame Copy Permalink