e8e2b88f5f
The 1st generation MediaTek PCIe host bridge cannot handle Message Signaled Interrupts (MSIs). The core PCI code is not aware that MSI is not available. This results in warnings of the form: WARNING: CPU: 2 PID: 112 at include/linux/msi.h:219 pci_msi_setup_msi_irqs.constprop.8+0x64/0x6c Modules linked in: ahci(+) libahci libata sd_mod scsi_mod gpio_button_hotplug CPU: 2 PID: 112 Comm: kmodloader Not tainted 5.10.52 #0 Hardware name: Mediatek Cortex-A7 (Device Tree) Import patches that introduce the 'no_msi' attribute to signal missing MSI support to the core PCI. Refresh patches: - 000-spi-fix-fifo.patch - 330-mtk-bmt-support.patch - 510-net-mediatek-add-flow-offload-for-mt7623.patch - 601-PCI-mediatek-Use-regmap-to-get-shared-pcie-cfg-base.patch - 610-pcie-mediatek-fix-clearing-interrupt-status.patch - 700-net-ethernet-mtk_eth_soc-add-support-for-coherent-DM.patch - 710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch Signed-off-by: Nick Hainke <vincent@systemli.org>
50 lines
1.7 KiB
Diff
50 lines
1.7 KiB
Diff
From 3a70dd2d050331ee4cf5ad9d5c0a32d83ead9a43 Mon Sep 17 00:00:00 2001
|
|
From: Peter Hess <peter.hess@ph-home.de>
|
|
Date: Tue, 6 Jul 2021 14:16:09 +0200
|
|
Subject: spi: mediatek: fix fifo rx mode
|
|
|
|
In FIFO mode were two problems:
|
|
- RX mode was never handled and
|
|
- in this case the tx_buf pointer was NULL and caused an exception
|
|
|
|
fix this by handling RX mode in mtk_spi_fifo_transfer
|
|
|
|
Fixes: a568231f4632 ("spi: mediatek: Add spi bus for Mediatek MT8173")
|
|
Signed-off-by: Peter Hess <peter.hess@ph-home.de>
|
|
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
|
|
Link: https://lore.kernel.org/r/20210706121609.680534-1-linux@fw-web.de
|
|
Signed-off-by: Mark Brown <broonie@kernel.org>
|
|
---
|
|
drivers/spi/spi-mt65xx.c | 16 +++++++++++++---
|
|
1 file changed, 13 insertions(+), 3 deletions(-)
|
|
|
|
--- a/drivers/spi/spi-mt65xx.c
|
|
+++ b/drivers/spi/spi-mt65xx.c
|
|
@@ -434,13 +434,23 @@ static int mtk_spi_fifo_transfer(struct
|
|
mtk_spi_setup_packet(master);
|
|
|
|
cnt = xfer->len / 4;
|
|
- iowrite32_rep(mdata->base + SPI_TX_DATA_REG, xfer->tx_buf, cnt);
|
|
+ if (xfer->tx_buf)
|
|
+ iowrite32_rep(mdata->base + SPI_TX_DATA_REG, xfer->tx_buf, cnt);
|
|
+
|
|
+ if (xfer->rx_buf)
|
|
+ ioread32_rep(mdata->base + SPI_RX_DATA_REG, xfer->rx_buf, cnt);
|
|
|
|
remainder = xfer->len % 4;
|
|
if (remainder > 0) {
|
|
reg_val = 0;
|
|
- memcpy(®_val, xfer->tx_buf + (cnt * 4), remainder);
|
|
- writel(reg_val, mdata->base + SPI_TX_DATA_REG);
|
|
+ if (xfer->tx_buf) {
|
|
+ memcpy(®_val, xfer->tx_buf + (cnt * 4), remainder);
|
|
+ writel(reg_val, mdata->base + SPI_TX_DATA_REG);
|
|
+ }
|
|
+ if (xfer->rx_buf) {
|
|
+ reg_val = readl(mdata->base + SPI_RX_DATA_REG);
|
|
+ memcpy(xfer->rx_buf + (cnt * 4), ®_val, remainder);
|
|
+ }
|
|
}
|
|
|
|
mtk_spi_enable_transfer(master);
|