uboot-rockchip-rk3588: Switch to v2017.09
This commit is contained in:
baiywt
parent
c7ef92382c
commit
f07e90c781
@ -5,12 +5,11 @@
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include $(TOPDIR)/rules.mk
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include $(INCLUDE_DIR)/kernel.mk
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PKG_VERSION:=2023.04
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PKG_RELEASE:=$(AUTORELEASE)
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PKG_HASH:=e31cac91545ff41b71cec5d8c22afd695645cd6e2a442ccdacacd60534069341
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PKG_MAINTAINER:=Tobias Maedel <openwrt@tbspace.de>
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PKG_SOURCE_PROTO:=git
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PKG_SOURCE_URL=https://github.com/orangepi-xunlong/u-boot-orangepi
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PKG_SOURCE_DATE:=2017-09
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PKG_SOURCE_VERSION:=d7c6b92f9e33283bea56dbaec7743f5ecb5a7f89
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PKG_MIRROR_HASH:=9c0d83c1a01a48173e47f63f7cb292347f0cebf4f0396d98616e0bfd5ce6f3fc
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include $(INCLUDE_DIR)/u-boot.mk
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include $(INCLUDE_DIR)/package.mk
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@ -42,9 +41,8 @@ UBOOT_TARGETS := \
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UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes
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UBOOT_MAKE_FLAGS += \
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PATH=$(PATH):$(STAGING_DIR_HOST)/bin \
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BL31=$(STAGING_DIR_IMAGE)/$(ATF) \
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ROCKCHIP_TPL=$(STAGING_DIR_IMAGE)/$(TPL)
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spl/u-boot-spl.bin u-boot.dtb u-boot.itb
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define Build/Configure
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$(call Build/Configure/U-Boot)
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@ -55,6 +53,8 @@ endef
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define Build/InstallDev
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$(INSTALL_DIR) $(STAGING_DIR_IMAGE)
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$(PKG_BUILD_DIR)/tools/mkimage -n rk3588 -T rksd -d \
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$(STAGING_DIR_IMAGE)/$(TPL):$(PKG_BUILD_DIR)/spl/u-boot-spl.bin $(PKG_BUILD_DIR)/idbloader.img
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$(CP) $(PKG_BUILD_DIR)/idbloader.img $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-idbloader.img
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$(CP) $(PKG_BUILD_DIR)/u-boot.itb $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-u-boot.itb
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endef
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File diff suppressed because it is too large
Load Diff
@ -1,320 +0,0 @@
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From 9a5e2f804caf676d4bdec794d68afaa86a3ceb2d Mon Sep 17 00:00:00 2001
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From: baiywt <baiywt_gj@163.com>
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Date: Thu, 13 Apr 2023 10:30:00 +0800
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Subject: [PATCH] Add support for orangepi5
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---
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arch/arm/dts/Makefile | 3 +-
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arch/arm/dts/rk3588s-orangepi-5-u-boot.dtsi | 127 ++++++++++++++++++++
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arch/arm/dts/rk3588s-orangepi-5.dts | 44 +++++++
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configs/orangepi-5-rk3588_defconfig | 99 +++++++++++++++
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4 files changed, 272 insertions(+), 1 deletion(-)
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create mode 100644 arch/arm/dts/rk3588s-orangepi-5-u-boot.dtsi
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create mode 100644 arch/arm/dts/rk3588s-orangepi-5.dts
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create mode 100644 configs/orangepi-5-rk3588_defconfig
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diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
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index 97a48327..acafd995 100644
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--- a/arch/arm/dts/Makefile
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+++ b/arch/arm/dts/Makefile
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@@ -171,7 +171,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
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dtb-$(CONFIG_ROCKCHIP_RK3588) += \
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rk3588-edgeble-neu6a-io.dtb \
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- rk3588-rock-5b.dtb
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+ rk3588-rock-5b.dtb \
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+ rk3588s-orangepi-5.dtb
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dtb-$(CONFIG_ROCKCHIP_RV1108) += \
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rv1108-elgin-r1.dtb \
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diff --git a/arch/arm/dts/rk3588s-orangepi-5-u-boot.dtsi b/arch/arm/dts/rk3588s-orangepi-5-u-boot.dtsi
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new file mode 100644
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index 00000000..7aca35ae
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--- /dev/null
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+++ b/arch/arm/dts/rk3588s-orangepi-5-u-boot.dtsi
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@@ -0,0 +1,127 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+/*
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+ * Copyright (c) 2023 Collabora Ltd.
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+ */
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+
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+#include "rk3588-u-boot.dtsi"
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+#include <dt-bindings/pinctrl/rockchip.h>
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+#include <dt-bindings/input/input.h>
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+#include <dt-bindings/gpio/gpio.h>
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+
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+/ {
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+ aliases {
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+ mmc0 = &sdmmc;
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+ };
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+
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+ chosen {
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+ u-boot,spl-boot-order = &sdmmc, "same-as-spl";
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+ u-boot,spl-boot-order = &sdmmc, "same-as-spl", &flash0;
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+ };
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+};
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+
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+&fspim2_pins {
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+ u-boot,dm-spl;
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+};
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+
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+&sdmmc {
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+ bus-width = <4>;
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+ bootph-all;
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+ u-boot,spl-fifo-mode;
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+ status = "okay";
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+};
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+
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+&pcfg_pull_up_drv_level_2 {
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+ bootph-all;
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+};
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+
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+&pcfg_pull_up {
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+ bootph-all;
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+};
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+
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+&sdmmc_bus4 {
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+ bootph-all;
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+};
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+
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+&sdmmc_clk {
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+ bootph-all;
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+};
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+
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+&sdmmc_cmd {
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+ bootph-all;
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+};
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+
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+&sdmmc_det {
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+ bootph-all;
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+};
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+
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+&usb_host0_ehci {
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+ companion = <&usb_host0_ohci>;
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+ phys = <&u2phy2_host>;
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+ phy-names = "usb2-phy";
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+ status = "okay";
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+};
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+
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+&usb_host0_ohci {
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+ phys = <&u2phy2_host>;
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+ phy-names = "usb2-phy";
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+ status = "okay";
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+};
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+
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+&usb2phy2_grf {
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+ status = "okay";
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+};
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+
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+&u2phy2 {
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+ resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
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+ reset-names = "phy", "apb";
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+ clock-output-names = "usb480m_phy2";
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+ status = "okay";
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+};
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+
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+&u2phy2_host {
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+ status = "okay";
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+};
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+
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+&usb_host1_ehci {
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+ companion = <&usb_host1_ohci>;
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+ phys = <&u2phy3_host>;
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+ phy-names = "usb2-phy";
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+ status = "okay";
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+};
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+
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+&usb_host1_ohci {
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+ phys = <&u2phy3_host>;
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+ phy-names = "usb2-phy";
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+ status = "okay";
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+};
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+
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+&usb2phy3_grf {
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+ status = "okay";
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+};
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+
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+&u2phy3 {
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+ resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
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+ reset-names = "phy", "apb";
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+ clock-output-names = "usb480m_phy3";
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+ status = "okay";
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+};
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+
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+&u2phy3_host {
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+ status = "okay";
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+};
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+
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+&sfc {
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+ bootph-all;
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+ pinctrl-0 = <&fspim2_pins>;
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+ pinctrl-names = "default";
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+ status = "okay";
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+
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+ flash0: flash@0 {
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+ bootph-all;
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+ compatible = "jedec,spi-nor";
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+ reg = <0>;
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+ spi-max-frequency = <10000000>;
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+ spi-rx-bus-width = <4>;
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+ spi-tx-bus-width = <1>;
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+ };
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+};
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diff --git a/arch/arm/dts/rk3588s-orangepi-5.dts b/arch/arm/dts/rk3588s-orangepi-5.dts
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new file mode 100644
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index 00000000..cf5743bc
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--- /dev/null
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+++ b/arch/arm/dts/rk3588s-orangepi-5.dts
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@@ -0,0 +1,44 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+
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+/dts-v1/;
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+
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+#include "rk3588s.dtsi"
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+
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+/ {
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+ model = "RK3588S Orange Pi 5";
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+ compatible = "xunlong,orangepi5", "rockchip,rk3588";
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+
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+ aliases {
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+ mmc0 = &sdhci;
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+ serial2 = &uart2;
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+ };
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+
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+ chosen {
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+ stdout-path = "serial2:1500000n8";
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+ };
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+
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+ vcc5v0_sys: vcc5v0-sys-regulator {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc5v0_sys";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <5000000>;
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+ regulator-max-microvolt = <5000000>;
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+ };
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+};
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+
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+&sdhci {
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+ bus-width = <8>;
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+ no-sdio;
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+ no-sd;
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+ non-removable;
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+ max-frequency = <200000000>;
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+ mmc-hs400-1_8v;
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+ mmc-hs400-enhanced-strobe;
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+ status = "okay";
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+};
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+
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+&uart2 {
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+ pinctrl-0 = <&uart2m0_xfer>;
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+ status = "okay";
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+};
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diff --git a/configs/orangepi-5-rk3588_defconfig b/configs/orangepi-5-rk3588_defconfig
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new file mode 100644
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index 00000000..782a4918
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--- /dev/null
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+++ b/configs/orangepi-5-rk3588_defconfig
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@@ -0,0 +1,99 @@
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+CONFIG_ARM=y
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+CONFIG_SKIP_LOWLEVEL_INIT=y
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+CONFIG_COUNTER_FREQUENCY=24000000
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+CONFIG_ARCH_ROCKCHIP=y
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+CONFIG_TEXT_BASE=0x00a00000
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+CONFIG_SPL_LIBCOMMON_SUPPORT=y
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+CONFIG_SPL_LIBGENERIC_SUPPORT=y
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+CONFIG_NR_DRAM_BANKS=2
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+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
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+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
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+CONFIG_DEFAULT_DEVICE_TREE="rk3588s-orangepi-5"
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+CONFIG_DM_RESET=y
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+CONFIG_ROCKCHIP_RK3588=y
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+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
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+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
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+CONFIG_SPL_MMC=y
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+CONFIG_ROCKCHIP_SPI_IMAGE=y
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+CONFIG_SPL_SERIAL=y
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+CONFIG_SPL_STACK_R_ADDR=0x600000
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+CONFIG_TARGET_ROCK5B_RK3588=y
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+CONFIG_SPL_STACK=0x400000
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+CONFIG_DEBUG_UART_BASE=0xFEB50000
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+CONFIG_DEBUG_UART_CLOCK=24000000
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+CONFIG_SPL_SPI_FLASH_SUPPORT=y
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+CONFIG_SPL_SPI=y
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+CONFIG_SYS_LOAD_ADDR=0xc00800
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+CONFIG_DEBUG_UART=y
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+CONFIG_FIT=y
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+CONFIG_FIT_VERBOSE=y
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+CONFIG_SPL_FIT_SIGNATURE=y
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+CONFIG_SPL_LOAD_FIT=y
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+CONFIG_OF_BOARD_SETUP=y
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+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-rock-5b.dtb"
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+# CONFIG_DISPLAY_CPUINFO is not set
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+CONFIG_DISPLAY_BOARDINFO_LATE=y
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+CONFIG_SPL_MAX_SIZE=0x20000
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+CONFIG_SPL_PAD_TO=0x7f8000
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+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
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+CONFIG_SPL_BSS_START_ADDR=0x4000000
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+CONFIG_SPL_BSS_MAX_SIZE=0x4000
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+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
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+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
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+CONFIG_SPL_STACK_R=y
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+CONFIG_SPL_SPI_LOAD=y
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+CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
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+CONFIG_SPL_ATF=y
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+CONFIG_CMD_GPIO=y
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+CONFIG_CMD_GPT=y
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+CONFIG_CMD_MMC=y
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+CONFIG_CMD_SPI=y
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+CONFIG_CMD_USB=y
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+# CONFIG_CMD_SETEXPR is not set
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+CONFIG_CMD_REGULATOR=y
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+# CONFIG_SPL_DOS_PARTITION is not set
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+CONFIG_SPL_OF_CONTROL=y
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+CONFIG_OF_LIVE=y
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+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
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+CONFIG_NET_RANDOM_ETHADDR=y
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+CONFIG_SPL_REGMAP=y
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+CONFIG_SPL_SYSCON=y
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+CONFIG_SPL_CLK=y
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+CONFIG_ROCKCHIP_GPIO=y
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+CONFIG_SYS_I2C_ROCKCHIP=y
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+CONFIG_MISC=y
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+CONFIG_SUPPORT_EMMC_RPMB=y
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+CONFIG_MMC_DW=y
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+CONFIG_MMC_DW_ROCKCHIP=y
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+CONFIG_MMC_SDHCI=y
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+CONFIG_MMC_SDHCI_SDMA=y
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+CONFIG_MMC_SDHCI_ROCKCHIP=y
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+CONFIG_SPI_FLASH_MACRONIX=y
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+CONFIG_ETH_DESIGNWARE=y
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+CONFIG_GMAC_ROCKCHIP=y
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+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
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+CONFIG_SPL_PINCTRL=y
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+CONFIG_REGULATOR_PWM=y
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+CONFIG_DM_REGULATOR_FIXED=y
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+CONFIG_PWM_ROCKCHIP=y
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+CONFIG_SPL_RAM=y
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+CONFIG_BAUDRATE=1500000
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+CONFIG_DEBUG_UART_SHIFT=2
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+CONFIG_ROCKCHIP_SFC=y
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+CONFIG_SYSRESET=y
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+# CONFIG_BINMAN_FDT is not set
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+CONFIG_USB=y
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+CONFIG_USB_EHCI_HCD=y
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+CONFIG_USB_EHCI_GENERIC=y
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+CONFIG_USB_OHCI_HCD=y
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+CONFIG_USB_OHCI_GENERIC=y
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+CONFIG_USB_HOST_ETHER=y
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+CONFIG_USB_ETHER_ASIX=y
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+CONFIG_USB_ETHER_ASIX88179=y
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+CONFIG_USB_ETHER_LAN75XX=y
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+CONFIG_USB_ETHER_LAN78XX=y
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+CONFIG_USB_ETHER_MCS7830=y
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+CONFIG_USB_ETHER_RTL8152=y
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+CONFIG_USB_ETHER_SMSC95XX=y
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+CONFIG_ERRNO_STR=y
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+CONFIG_LEGACY_IMAGE_FORMAT=y
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--
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2.25.1
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@ -0,0 +1,66 @@
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From ea133a0b014abc21ac8919e6e370a463784b909b Mon Sep 17 00:00:00 2001
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From: baiywt <baiywt_gj@163.com>
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Date: Wed, 26 Apr 2023 18:25:06 +0800
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Subject: [PATCH 1/4] Revert "gpt: return 1 directly when test the mbr sector"
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This reverts commit https://github.com/rockchip-linux/u-boot/commit/3bdef7e642ae558d0e61ce26438d10b55b26ec9c
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Reason: It causes recognition errors when the partition is not gpt
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---
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disk/part_efi.c | 18 +-----------------
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1 file changed, 1 insertion(+), 17 deletions(-)
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diff --git a/disk/part_efi.c b/disk/part_efi.c
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index 0ec1bef..2ad5f9c 100644
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--- a/disk/part_efi.c
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+++ b/disk/part_efi.c
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@@ -445,7 +445,6 @@ static int part_efi_repair(struct blk_desc *dev_desc, gpt_entry *gpt_pte,
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static int part_test_efi(struct blk_desc *dev_desc)
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{
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ALLOC_CACHE_ALIGN_BUFFER_PAD(legacy_mbr, legacymbr, 1, dev_desc->blksz);
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- int ret = 0;
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/* Read legacy MBR from block 0 and validate it */
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if ((blk_dread(dev_desc, 0, 1, (ulong *)legacymbr) != 1)
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@@ -489,10 +488,7 @@ static int part_test_efi(struct blk_desc *dev_desc)
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if (part_efi_repair(dev_desc, b_gpt_pte, b_gpt_head,
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head_gpt_valid, backup_gpt_valid))
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printf("Primary GPT repair fail!\n");
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- } else if (head_gpt_valid == 0 && backup_gpt_valid == 0) {
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- ret = -1;
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}
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-
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free(h_gpt_pte);
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h_gpt_pte = NULL;
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free(h_gpt_head);
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@@ -503,7 +499,7 @@ static int part_test_efi(struct blk_desc *dev_desc)
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b_gpt_head = NULL;
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#endif
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#endif
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- return ret;
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+ return 0;
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}
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/**
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@@ -1083,18 +1079,6 @@ static int is_pmbr_valid(legacy_mbr * mbr)
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{
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int i = 0;
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-#ifdef CONFIG_ARCH_ROCKCHIP
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- /*
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||||
- * In sd-update card, we use RKPARM partition in bootloader to load
|
||||
- * firmware, and use MS-DOS partition in recovery to update system.
|
||||
- * Now, we want to use gpt in bootloader and abandon the RKPARM
|
||||
- * partition. So in new sd-update card, we write the MS-DOS partition
|
||||
- * table and gpt to sd card. Then we must return 1 directly when test
|
||||
- * the mbr sector otherwise the gpt is unavailable.
|
||||
- */
|
||||
- return 1;
|
||||
-#endif
|
||||
-
|
||||
if (!mbr || le16_to_cpu(mbr->signature) != MSDOS_MBR_SIGNATURE)
|
||||
return 0;
|
||||
|
||||
--
|
||||
2.25.1
|
||||
|
||||
@ -0,0 +1,274 @@
|
||||
From 62caaf649a013429c2c7b08ddb70b82c95ef278a Mon Sep 17 00:00:00 2001
|
||||
From: baiywt <baiywt_gj@163.com>
|
||||
Date: Wed, 26 Apr 2023 18:37:05 +0800
|
||||
Subject: [PATCH 3/4] configs: Add new orangepi-5-rk3588_defconfig for openwrt
|
||||
|
||||
---
|
||||
configs/orangepi-5-rk3588_defconfig | 255 ++++++++++++++++++++++++++++
|
||||
1 file changed, 255 insertions(+)
|
||||
create mode 100644 configs/orangepi-5-rk3588_defconfig
|
||||
|
||||
diff --git a/configs/orangepi-5-rk3588_defconfig b/configs/orangepi-5-rk3588_defconfig
|
||||
new file mode 100644
|
||||
index 0000000..5a71f98
|
||||
--- /dev/null
|
||||
+++ b/configs/orangepi-5-rk3588_defconfig
|
||||
@@ -0,0 +1,255 @@
|
||||
+CONFIG_ARM=y
|
||||
+CONFIG_ARCH_ROCKCHIP=y
|
||||
+CONFIG_SPL_GPIO_SUPPORT=y
|
||||
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
+CONFIG_SYS_MALLOC_F_LEN=0x80000
|
||||
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.sh"
|
||||
+CONFIG_ROCKCHIP_RK3588=y
|
||||
+CONFIG_ROCKCHIP_FIT_IMAGE=y
|
||||
+CONFIG_ROCKCHIP_HWID_DTB=y
|
||||
+CONFIG_ROCKCHIP_VENDOR_PARTITION=y
|
||||
+CONFIG_ROCKCHIP_FIT_IMAGE_PACK=y
|
||||
+CONFIG_ROCKCHIP_NEW_IDB=y
|
||||
+CONFIG_LOADER_INI="RK3588MINIALL.ini"
|
||||
+CONFIG_TRUST_INI="RK3588TRUST.ini"
|
||||
+CONFIG_PSTORE=y
|
||||
+CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
||||
+CONFIG_TARGET_EVB_RK3588=y
|
||||
+CONFIG_SPL_LIBDISK_SUPPORT=y
|
||||
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||
+CONFIG_SPL_SPI_SUPPORT=y
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="rk3588s-orangepi-5"
|
||||
+CONFIG_DEBUG_UART=y
|
||||
+CONFIG_FIT=y
|
||||
+CONFIG_FIT_IMAGE_POST_PROCESS=y
|
||||
+CONFIG_FIT_HW_CRYPTO=y
|
||||
+CONFIG_SPL_LOAD_FIT=y
|
||||
+CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
|
||||
+CONFIG_SPL_FIT_HW_CRYPTO=y
|
||||
+# CONFIG_SPL_SYS_DCACHE_OFF is not set
|
||||
+CONFIG_BOOTDELAY=0
|
||||
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
|
||||
+# CONFIG_DISPLAY_CPUINFO is not set
|
||||
+CONFIG_ANDROID_BOOTLOADER=y
|
||||
+CONFIG_ANDROID_AVB=y
|
||||
+CONFIG_ANDROID_BOOT_IMAGE_HASH=y
|
||||
+CONFIG_SPL_BOARD_INIT=y
|
||||
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
|
||||
+CONFIG_SPL_SEPARATE_BSS=y
|
||||
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
|
||||
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x1
|
||||
+CONFIG_SPL_MMC_WRITE=y
|
||||
+CONFIG_SPL_MTD_SUPPORT=y
|
||||
+CONFIG_SPL_ATF=y
|
||||
+CONFIG_FASTBOOT_BUF_ADDR=0xc00800
|
||||
+CONFIG_FASTBOOT_BUF_SIZE=0x07000000
|
||||
+CONFIG_FASTBOOT_FLASH=y
|
||||
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
|
||||
+CONFIG_CMD_BOOTZ=y
|
||||
+CONFIG_CMD_DTIMG=y
|
||||
+# CONFIG_CMD_ELF is not set
|
||||
+# CONFIG_CMD_IMI is not set
|
||||
+# CONFIG_CMD_IMLS is not set
|
||||
+# CONFIG_CMD_XIMG is not set
|
||||
+# CONFIG_CMD_LZMADEC is not set
|
||||
+# CONFIG_CMD_UNZIP is not set
|
||||
+# CONFIG_CMD_FLASH is not set
|
||||
+# CONFIG_CMD_FPGA is not set
|
||||
+CONFIG_CMD_GPT=y
|
||||
+# CONFIG_CMD_LOADB is not set
|
||||
+# CONFIG_CMD_LOADS is not set
|
||||
+CONFIG_CMD_BOOT_ANDROID=y
|
||||
+CONFIG_CMD_MMC=y
|
||||
+CONFIG_CMD_PCI=y
|
||||
+CONFIG_CMD_SF=y
|
||||
+CONFIG_CMD_SPI=y
|
||||
+CONFIG_CMD_USB=y
|
||||
+CONFIG_CMD_USB_MASS_STORAGE=y
|
||||
+# CONFIG_CMD_ITEST is not set
|
||||
+# CONFIG_CMD_SETEXPR is not set
|
||||
+CONFIG_CMD_TFTPPUT=y
|
||||
+CONFIG_CMD_TFTP_BOOTM=y
|
||||
+CONFIG_CMD_TFTP_FLASH=y
|
||||
+# CONFIG_CMD_MISC is not set
|
||||
+CONFIG_CMD_MTD_BLK=y
|
||||
+# CONFIG_SPL_DOS_PARTITION is not set
|
||||
+# CONFIG_ISO_PARTITION is not set
|
||||
+CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
|
||||
+CONFIG_SPL_OF_CONTROL=y
|
||||
+CONFIG_SPL_DTB_MINIMUM=y
|
||||
+CONFIG_OF_LIVE=y
|
||||
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
+CONFIG_OF_U_BOOT_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
+# CONFIG_NET_TFTP_VARS is not set
|
||||
+CONFIG_REGMAP=y
|
||||
+CONFIG_SPL_REGMAP=y
|
||||
+CONFIG_SYSCON=y
|
||||
+CONFIG_SPL_SYSCON=y
|
||||
+# CONFIG_SARADC_ROCKCHIP is not set
|
||||
+CONFIG_SARADC_ROCKCHIP_V2=y
|
||||
+CONFIG_CLK=y
|
||||
+CONFIG_SPL_CLK=y
|
||||
+CONFIG_CLK_SCMI=y
|
||||
+CONFIG_SPL_CLK_SCMI=y
|
||||
+CONFIG_DM_CRYPTO=y
|
||||
+CONFIG_SPL_DM_CRYPTO=y
|
||||
+CONFIG_ROCKCHIP_CRYPTO_V2=y
|
||||
+CONFIG_SPL_ROCKCHIP_CRYPTO_V2=y
|
||||
+CONFIG_DM_RNG=y
|
||||
+CONFIG_RNG_ROCKCHIP=y
|
||||
+CONFIG_SCMI_FIRMWARE=y
|
||||
+CONFIG_SPL_SCMI_FIRMWARE=y
|
||||
+CONFIG_GPIO_HOG=y
|
||||
+CONFIG_ROCKCHIP_GPIO=y
|
||||
+CONFIG_ROCKCHIP_GPIO_V2=y
|
||||
+CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
+CONFIG_I2C_MUX=y
|
||||
+CONFIG_DM_KEY=y
|
||||
+CONFIG_RK8XX_PWRKEY=y
|
||||
+CONFIG_ADC_KEY=y
|
||||
+CONFIG_MISC=y
|
||||
+CONFIG_SPL_MISC=y
|
||||
+CONFIG_MISC_DECOMPRESS=y
|
||||
+CONFIG_SPL_MISC_DECOMPRESS=y
|
||||
+CONFIG_ROCKCHIP_OTP=y
|
||||
+CONFIG_ROCKCHIP_HW_DECOMPRESS=y
|
||||
+CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS=y
|
||||
+CONFIG_SPL_ROCKCHIP_SECURE_OTP=y
|
||||
+CONFIG_MMC_DW=y
|
||||
+CONFIG_MMC_DW_ROCKCHIP=y
|
||||
+CONFIG_MMC_SDHCI=y
|
||||
+CONFIG_MMC_SDHCI_SDMA=y
|
||||
+CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
+CONFIG_MTD=y
|
||||
+CONFIG_MTD_BLK=y
|
||||
+CONFIG_MTD_DEVICE=y
|
||||
+CONFIG_NAND=y
|
||||
+CONFIG_MTD_SPI_NAND=y
|
||||
+CONFIG_SPI_FLASH=y
|
||||
+CONFIG_SF_DEFAULT_SPEED=80000000
|
||||
+CONFIG_SPI_FLASH_EON=y
|
||||
+CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
+CONFIG_SPI_FLASH_MACRONIX=y
|
||||
+CONFIG_SPI_FLASH_SST=y
|
||||
+CONFIG_SPI_FLASH_WINBOND=y
|
||||
+CONFIG_SPI_FLASH_XMC=y
|
||||
+CONFIG_SPI_FLASH_XTX=y
|
||||
+CONFIG_SPI_FLASH_MTD=y
|
||||
+CONFIG_DM_ETH=y
|
||||
+CONFIG_DM_ETH_PHY=y
|
||||
+CONFIG_DWC_ETH_QOS=y
|
||||
+CONFIG_GMAC_ROCKCHIP=y
|
||||
+CONFIG_NVME=y
|
||||
+CONFIG_PCI=y
|
||||
+CONFIG_DM_PCI=y
|
||||
+CONFIG_DM_PCI_COMPAT=y
|
||||
+CONFIG_PCIE_DW_ROCKCHIP=y
|
||||
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
+CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX=y
|
||||
+CONFIG_PHY_ROCKCHIP_USBDP=y
|
||||
+CONFIG_PINCTRL=y
|
||||
+CONFIG_SPL_PINCTRL=y
|
||||
+CONFIG_DM_FUEL_GAUGE=y
|
||||
+CONFIG_POWER_FG_CW201X=y
|
||||
+CONFIG_POWER_FG_CW221X=y
|
||||
+CONFIG_DM_PMIC=y
|
||||
+CONFIG_PMIC_SPI_RK8XX=y
|
||||
+CONFIG_DM_POWER_DELIVERY=y
|
||||
+CONFIG_TYPEC_TCPM=y
|
||||
+CONFIG_TYPEC_TCPCI=y
|
||||
+CONFIG_TYPEC_HUSB311=y
|
||||
+CONFIG_TYPEC_FUSB302=y
|
||||
+CONFIG_REGULATOR_PWM=y
|
||||
+CONFIG_DM_REGULATOR_FIXED=y
|
||||
+CONFIG_DM_REGULATOR_GPIO=y
|
||||
+CONFIG_REGULATOR_RK860X=y
|
||||
+CONFIG_REGULATOR_RK806=y
|
||||
+CONFIG_CHARGER_BQ25700=y
|
||||
+CONFIG_CHARGER_BQ25890=y
|
||||
+CONFIG_CHARGER_SC8551=y
|
||||
+CONFIG_CHARGER_SGM41542=y
|
||||
+CONFIG_DM_CHARGE_DISPLAY=y
|
||||
+CONFIG_CHARGE_ANIMATION=y
|
||||
+CONFIG_PWM_ROCKCHIP=y
|
||||
+CONFIG_RAM=y
|
||||
+CONFIG_SPL_RAM=y
|
||||
+CONFIG_TPL_RAM=y
|
||||
+CONFIG_DM_RAMDISK=y
|
||||
+CONFIG_RAMDISK_RO=y
|
||||
+CONFIG_DM_RESET=y
|
||||
+CONFIG_SPL_DM_RESET=y
|
||||
+CONFIG_SPL_RESET_ROCKCHIP=y
|
||||
+CONFIG_BAUDRATE=1500000
|
||||
+CONFIG_DEBUG_UART_BASE=0xFEB50000
|
||||
+CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
+CONFIG_DEBUG_UART_SHIFT=2
|
||||
+CONFIG_ROCKCHIP_SPI=y
|
||||
+CONFIG_ROCKCHIP_SFC=y
|
||||
+CONFIG_SYSRESET=y
|
||||
+CONFIG_USB=y
|
||||
+CONFIG_USB_XHCI_HCD=y
|
||||
+CONFIG_USB_XHCI_DWC3=y
|
||||
+CONFIG_USB_XHCI_PCI=y
|
||||
+CONFIG_USB_EHCI_HCD=y
|
||||
+CONFIG_USB_EHCI_GENERIC=y
|
||||
+CONFIG_USB_OHCI_HCD=y
|
||||
+CONFIG_USB_OHCI_GENERIC=y
|
||||
+CONFIG_USB_DWC3=y
|
||||
+CONFIG_USB_DWC3_GADGET=y
|
||||
+CONFIG_USB_DWC3_GENERIC=y
|
||||
+CONFIG_USB_STORAGE=y
|
||||
+CONFIG_USB_GADGET=y
|
||||
+CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
|
||||
+CONFIG_USB_GADGET_VENDOR_NUM=0x2207
|
||||
+CONFIG_USB_GADGET_PRODUCT_NUM=0x350a
|
||||
+CONFIG_USB_GADGET_DOWNLOAD=y
|
||||
+CONFIG_DM_VIDEO=y
|
||||
+CONFIG_DISPLAY=y
|
||||
+CONFIG_DRM_ROCKCHIP=y
|
||||
+CONFIG_DRM_MAXIM_MAX96745=y
|
||||
+CONFIG_DRM_MAXIM_MAX96752F=y
|
||||
+CONFIG_DRM_MAXIM_MAX96755F=y
|
||||
+CONFIG_DRM_PANEL_MAXIM_DESERIALIZER=y
|
||||
+CONFIG_DRM_ROHM_BU18XL82=y
|
||||
+CONFIG_DRM_ROCKCHIP_DW_HDMI_QP=y
|
||||
+CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI2=y
|
||||
+CONFIG_DRM_ROCKCHIP_ANALOGIX_DP=y
|
||||
+CONFIG_DRM_ROCKCHIP_DW_DP=y
|
||||
+CONFIG_DRM_ROCKCHIP_SAMSUNG_MIPI_DCPHY=y
|
||||
+CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX_HDMI=y
|
||||
+CONFIG_USE_TINY_PRINTF=y
|
||||
+CONFIG_LIB_RAND=y
|
||||
+CONFIG_SPL_TINY_MEMSET=y
|
||||
+CONFIG_RSA=y
|
||||
+CONFIG_SPL_RSA=y
|
||||
+CONFIG_RSA_N_SIZE=0x200
|
||||
+CONFIG_RSA_E_SIZE=0x10
|
||||
+CONFIG_RSA_C_SIZE=0x20
|
||||
+CONFIG_XBC=y
|
||||
+CONFIG_LZ4=y
|
||||
+CONFIG_LZMA=y
|
||||
+CONFIG_ERRNO_STR=y
|
||||
+# CONFIG_EFI_LOADER is not set
|
||||
+CONFIG_AVB_LIBAVB=y
|
||||
+CONFIG_AVB_LIBAVB_AB=y
|
||||
+CONFIG_AVB_LIBAVB_ATX=y
|
||||
+CONFIG_AVB_LIBAVB_USER=y
|
||||
+CONFIG_RK_AVB_LIBAVB_USER=y
|
||||
+CONFIG_OPTEE_CLIENT=y
|
||||
+CONFIG_OPTEE_V2=y
|
||||
+CONFIG_OPTEE_ALWAYS_USE_SECURITY_PARTITION=y
|
||||
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
|
||||
+CONFIG_CMD_SETEXPR=y
|
||||
+CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
|
||||
+CONFIG_SYS_PROMPT="opi# "
|
||||
+CONFIG_AHCI=y
|
||||
+CONFIG_CMD_SCSI=y
|
||||
+CONFIG_DM_SCSI=y
|
||||
+CONFIG_DWC_AHCI=y
|
||||
+CONFIG_LIBATA=y
|
||||
+CONFIG_SCSI_AHCI=y
|
||||
+CONFIG_SCSI=y
|
||||
+CONFIG_USING_KERNEL_DTB_V2=y
|
||||
--
|
||||
2.25.1
|
||||
|
||||
@ -1,10 +0,0 @@
|
||||
--- a/tools/Makefile
|
||||
+++ b/tools/Makefile
|
||||
@@ -113,7 +113,6 @@ dumpimage-mkimage-objs := aisimage.o \
|
||||
imximage.o \
|
||||
imx8image.o \
|
||||
imx8mimage.o \
|
||||
- kwbimage.o \
|
||||
lib/md5.o \
|
||||
lpc32xximage.o \
|
||||
mxsimage.o \
|
||||
@ -1,30 +0,0 @@
|
||||
--- a/Makefile
|
||||
+++ b/Makefile
|
||||
@@ -2000,26 +2000,7 @@ endif
|
||||
# Check dtc and pylibfdt, if DTC is provided, else build them
|
||||
PHONY += scripts_dtc
|
||||
scripts_dtc: scripts_basic
|
||||
- $(Q)if test "$(DTC)" = "$(DTC_INTREE)"; then \
|
||||
- $(MAKE) $(build)=scripts/dtc; \
|
||||
- else \
|
||||
- if ! $(DTC) -v >/dev/null; then \
|
||||
- echo '*** Failed to check dtc version: $(DTC)'; \
|
||||
- false; \
|
||||
- else \
|
||||
- if test "$(call dtc-version)" -lt $(DTC_MIN_VERSION); then \
|
||||
- echo '*** Your dtc is too old, please upgrade to dtc $(DTC_MIN_VERSION) or newer'; \
|
||||
- false; \
|
||||
- else \
|
||||
- if [ -n "$(CONFIG_PYLIBFDT)" ]; then \
|
||||
- if ! echo "import libfdt" | $(PYTHON3) 2>/dev/null; then \
|
||||
- echo '*** pylibfdt does not seem to be available with $(PYTHON3)'; \
|
||||
- false; \
|
||||
- fi; \
|
||||
- fi; \
|
||||
- fi; \
|
||||
- fi; \
|
||||
- fi
|
||||
+ $(MAKE) $(build)=scripts/dtc
|
||||
|
||||
# ---------------------------------------------------------------------------
|
||||
quiet_cmd_cpp_lds = LDS $@
|
||||
@ -1,24 +0,0 @@
|
||||
--- a/tools/image-host.c
|
||||
+++ b/tools/image-host.c
|
||||
@@ -1125,6 +1125,7 @@ static int fit_config_add_verification_d
|
||||
* 2) get public key (X509_get_pubkey)
|
||||
* 3) provide der format (d2i_RSAPublicKey)
|
||||
*/
|
||||
+#ifdef CONFIG_TOOLS_LIBCRYPTO
|
||||
static int read_pub_key(const char *keydir, const void *name,
|
||||
unsigned char **pubkey, int *pubkey_len)
|
||||
{
|
||||
@@ -1178,6 +1179,13 @@ err_cert:
|
||||
fclose(f);
|
||||
return ret;
|
||||
}
|
||||
+#else
|
||||
+static int read_pub_key(const char *keydir, const void *name,
|
||||
+ unsigned char **pubkey, int *pubkey_len)
|
||||
+{
|
||||
+ return -ENOSYS;
|
||||
+}
|
||||
+#endif
|
||||
|
||||
int fit_pre_load_data(const char *keydir, void *keydest, void *fit)
|
||||
{
|
||||
Loading…
x
Reference in New Issue
Block a user